 | | ALINTô is a VHDL and Verilog Design Rule Checking Tool used to analyze HDL source code against a comprehensive set of ASIC design guidelines for early bug detection, cross-probing |
| 64-channel CMOS digital I/O module |
| Active-HDL is a powerful mixed-language simulator with tools for graphical design entry, project management, HDL verification and documentation |
| The DO-254 CTS consists of a mixed language HDL Simulation tool suite and In-Hardware Simulation system that supports the customer's specific FPGA, PLD, or ASIC target device provi |
| Family of off-the-shelf products designed to work with Talon SR-192 (192-channel dynamic digital I/O module) |
| HES (Hardware Emulation System) may be used for emulation, acceleration and prototyping |
| The Fusion TCP/IPv4/v6 Stack protocol suite provides developers a highly portable source code stack designed specifically for embedded applications |
| Model KPXI-SYS-6-250 3U PXI 6-Slot Instrument Chassis with 250W AC Power |
| Table Driven with up to 500,000 User Programmed Pulse Delay/Width Entries per Channel |
| Model KPXI-DAQ-64-250K 64-Channel, 250KS/s, 16-Bit, Multifunction PXI Module |
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