 | | The RTXCview product consists of two parts: a Recorder in the RTXC kernel, which logs system and user events in target RAM, and a viewer, which runs on a host PC |
| In addition to including the Spartan-6 FPGA, the LX9 FPGA MicroBoard also includes low-power DDR memory, an Ethernet port, programmable clock and two expansion ports for I/O access |
| Performance boost and greater flexibility through unified cross platform middleware and FPGA based I/O design services |
| Objective Interface Systems, Inc. (OIS), the leading provider of real-time, embedded and high-performance middleware communications solutions, today announced the introduction of the OIS Automotive Reference Platform with ORBexpress. |
| ARBOR Technology, a leading provider of embedded, medical and tablet computing, has unveiled a latest compact board – EmCORE-i2902, which adopts EPIC form factor and built-in Intel Atom N450 processor and ICH8M chipset, as well as 1GB soldered DDR2 SDRAM. Atom D510 processor is also selectable in terms of customer’s requirement. The target applications include industrial automation, security control, government sector and transportation. |
| Microtronix has enhanced their Multi-port SDRAM Memory Controller IP Core, to support Mobile DDR memory devices on Cyclone IV family of FPGAs. Microtronix offers designers a free 1-year evaluation license to build and test hardware designs on the low-cost BeMicro SDK. IP Core licenses are available online for immediate download. |
| For flexible display connection, COM Revision 2.0 leaves dedicated pins for new DDI (Digital Display Interfaces). A new software extension has also been introduced with COM.0 Revision 2.0: EAPI (Embedded Application Programming Interface). |
| OP5142 Reconfigurable FPGA-based I/O Controller enables distributed execution of Hardware Description Language (HDL) functions and high-speed, high-density digital I/O in real-time models |
| Development with new Intel(r) processor and platform controller hub extends options for board and system-level solutions |
| Time to Prototype, Stage Delay and Hardware Usage Optimized by Well Integrated Tools and High-Memory, High-Throughput FPGA-Based Hardware |
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