 | | A low-cost, high-performance DSP optimized for cost sensitive consumer audio applications |
| A device that allows the host debug system to communicate with a Motorola DSP target system through the JTAG/OnCE connector |
| A DSP core based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle |
| A 24-bit digital processor that supports network applications with general filtering operations |
| A 24-bit DSP intended for general-purpose digital signal processing, particularly in multimedia and telecommunication applications, such as videoconferencing and cellular telephony |
| A single-chip Power over Ethernet (PoE) solution that combines a powered device (PD) interface port (802.3af standard) and a pulse width modulator controller |
| Enables industry-leading solar cell startup and operating performance and efficiency at levels as low as 0.32 volts, as well as operation down to 0.25 V |
| A 24-bit DSP intended for applications requiring a large amount of on-chip memory, such as wireless infrastructure applications |
| AEC-Q100 Grade 3 Qualification |
| A DSP based on the 24-bit DSP56300 architecture that uses the single-instruction-per-clock-cycle DSP56300 core, while retaining code compatibility with the DSP56000 core family |
| |
