 | | Provides users with single-chip solutions that integrate an industrial-grade dual-core 800 MHz ARM Cortex-A9 processor with Altera's 28 nm low-power Cyclone V and Arria V FPGAs |
| Internal clock frequency rates up to 500 MHz and typical performance >250 MHz |
| The HD WDR video surveillance chipset comprises an Altera Cyclone IV E FPGA loaded with image processing IP bolted to an image sensor, and it provides High Def Wide Dynamic Range plus logic security |
| Altera's EFEC7 and EFEC20 are ultra high gain, hard decision FEC cores that enhance 100G networks and provide the smallest FPGA-based EFEC implementation available in the industry today |
| Provide a new partial reconfiguration method |
| With the variable-precision DSP block, Altera’s Stratix V FPGA can support – on a block-by-block basis – various precisions ranging from 9-bit x 9-bit up to single-precision floating point (mantissa
multiplication) within a single DSP block |
| Up to 50 percent lower total power compared to other equivalent density CPLDs on the market |
| Achieves a static power figure of 0.25 W |
| Links MATLAB/Simulink tools with the Altera Quartus II design software |
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