Accellera, the electronics industry organization focused on electronic design automation (EDA) standards, today announced that its Board of Directors, representing systems, semiconductor and design tool member companies, approved Accellera’s Open Verification Library (OVL) 1.0, as an Accellera verification standard earlier this month. The new standard was also approved unanimously by the Accellera OVL Verilog/SystemVerilog Assertion (OVL-VSVA) technical committee.
The OVL standard results in better quality HDL (hardware description language) designs, since the pre-defined checkers, written in either Verilog or SystemVerilog, allow designers to take advantage of assertion-based verification immediately. Both SystemVerilog and Verilog language-compliant tools can take advantage of this new verification standard. The library includes 31 assertion checkers for each language that cover many of the common properties that engineers check during the functional verification of register-transfer level (RTL) code.
